Re: Utility of copper pours on four-layer boards
- From: "Joel Koltner" <zapwireDASHgroups@xxxxxxxxx>
- Date: Mon, 7 Apr 2008 15:17:58 -0700
"Joerg" <notthisjoergsch@xxxxxxxxxxxxxxxxxxxxx> wrote in message
news:FvvKj.2239$IF7.113@xxxxxxxxxxxxxxxxxxxxxxxxxxxxx
It provides some isolation between areas across from the pour. Or in RF
speak stuff "talks less".
Yeah, good point certainly... I wonder if I've ever "accidentally" benefitted
from this?
It's also an additional free capacitor if over the VCC plane.
OK.
Also, it lets you sneak a hidden yet well shielded trace underneath, by
cannibalizing a bit of the real GND plane or VCC. Just dunnit. Shhht ...
nobody can see it :-)
:-)
That does seem to be the best approach if you actually need lots of shielding,
although I've seen people shy away from it since it's of course that much
harder to probe.
Some years ago I was talking with a guy at a testing lab and he said they did
have one customer who would first make their engineering prototype boards the
"usual" way and then, once everything was working, re-spin them with power and
ground on the outside layers and signal layers on the inside.
Thanks Joerg,
---Joel
.
- Follow-Ups:
- Re: Utility of copper pours on four-layer boards
- From: Joerg
- Re: Utility of copper pours on four-layer boards
- References:
- Utility of copper pours on four-layer boards
- From: Joel Koltner
- Re: Utility of copper pours on four-layer boards
- From: Joerg
- Utility of copper pours on four-layer boards
- Prev by Date: current through FET
- Next by Date: Re: Utility of copper pours on four-layer boards
- Previous by thread: Re: Utility of copper pours on four-layer boards
- Next by thread: Re: Utility of copper pours on four-layer boards
- Index(es):