Re: active PFC input filter


"Jamie Morken" <jmorken@xxxxxxx> wrote in message news:tDSLj.171635$pM4.116965@xxxxxxxxxxxx
MooseFET wrote:
On Apr 10, 3:00 am, Jamie Morken <jmor...@xxxxxxx> wrote:
Hi,

I have a simulation of multiphase active power factor correction
for a 3.6kW battery charger, that generates a 380VDC bus from
either 120VAC single phase or 240VAC split phase. At 120VAC input
the output power is limited to 1.8kW to keep the required inductor
sizes lower.

There are three phases with each phase having a 75uH/25Amp inductor.

The base PWM frequency for the inductor boost switches is 200kHz,
with the pulses to each switch being offset by 1/3rd of the PWM
period.

Here is the schematic:http://rocketresearch.nekrom.com/new/multiphasePFC/multiphasePFCschem...

The only shunt being used for the PFC algorithm is the lowside shunt.

The input filter is just an LC lowpass on the output of the bridge
rectifier. The rectified current ripple is here:

http://rocketresearch.nekrom.com/new/multiphasePFC/60HzinputCurrent.jpg

I haven't been able to really reduce this current ripple to make a nice
signal showing good power factor. What is a better way to hook up a
filter for this type of circuit rather than using the LC filter on the
output of the bridge rectifier?

More stages of filtering may be the way to go. You are going to need
an EMI filter before the bridge to kill the harmonics the diodes
create so why not use a PI filter there to help the ripple reduction.

Hi,

I made a test PI filter in ltspice, it lets about 60mA of 300kHz current
ripple back to the AC source (V1 and V2 are 240VAC splitphase), any
suggestions on how to improve this filter, or is this a good
configuration to use?

http://rocketresearch.nekrom.com/new/multiphasePFC/PFC-input-filter.jpg

The cap before the first inductor, L1, doesn't seem to really do much in
the simulation, what is the reason for using a PI filter on the AC lines
rather than just an LC?

The right side of the schematic leads to the multiphase PFC stage.
The ripple is 300kHz as there are 3 100kHz boost circuits in parallel,
offset by 1/3rd.

cheers,
Jamie

Jamie, Jamie, do you have good medical insurance? I worry about you and my bottle of tequila. Your always playing in high voltage with both hands.
Filters have to do with input and output impedance over the frequency range of interest. Your poor C4 is in parallel with V1+V2 that have a Zout of maybe 1mR. For C4 to be of any worth it's Z must be much lower. In normal testing this unit will be plugged into a LISN that looks like 50R at 200KHz. To do any reasonable simulation you must add the LISN and line Zo to your simulation for both PFC and CE (Conducted Emissions).
If done properly you will end up with another inductor between V1 and C4. As you increase the size of C4+C5+C3 you are reducing the power factor because these components draw current that is phase shifted. C3 must be split into 3 caps, one for each phase and placed close to the switching FET to reduce large current loops. A max value for each cap is around 3.3uF for C4 and C5 (Special X caps) and maybe 1.0uF for each C3. Now increase the three inductors until proper attenuation is attained. Good idea to split the inductors into both sides of the line (balanced), four inductors total. Dump L5. Now if this filter has to pass PFC and CE you must make sure there are no large gain peaks at the 5, 7, +9 harmonic of the line frequency. Add D-Qing R+C to fix.
Now that the DM (Differential Mode) is filtered add the CM (common mode) section.
Where the hell is Genome, he normally handles this rookie s**t.
Got to go watch the sunset and drink some tequila.
Harry

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