Re: Formula for minimum drive current for mosfet

On Apr 12, 1:33 pm, "Jon Slaughter" <Jon_Slaugh...@xxxxxxxxxxx> wrote:
BTW, this should point to an optimal switching frequency for least power
dissipation? Anyone know the formula?

There is a point where the transistor no longer sees average power but
peak power. Never having designed in a power fet process, I don't know
the design rule. In more general purpose semiconductor processes, the
electromigration frequency limit is 1Khz. That is, a line that is
being pulsed that you wish to consider receiving average current
should be switching faster that 1KHz.

Power MOSFETs do have SOA limits, but it is not as critical as with
bipolars.

I like how you worry about everything. No, really. ;-) There is noting
worse than getting product returned.

If your intent is to drive directly from the uP, you may want to
consider how the load switching will effect the uP. You will probably
get ground bounce. In addition, as you increase VGS, there will be
current flow from CDG. If the drain voltage is falling like a rock, it
will generate current that opposes your gate drive. What I'm leading
to here is you should probably buffer the uP from the power fet.
.

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