Re: Formula for minimum drive current for mosfet


"gearhead" <nospam@xxxxxxxxxxxx> wrote in message
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On Apr 12, 7:54 pm, "Paul E. Schoen" <pst...@xxxxxxxxx> wrote:
<m...@xxxxxxxxx> wrote in message

news:3e667771-ed64-4a9e-a065-ced0e13f718f@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
On Apr 12, 1:33 pm, "Jon Slaughter" <Jon_Slaugh...@xxxxxxxxxxx> wrote:
BTW, this should point to an optimal switching frequency for least
power
dissipation? Anyone know the formula?

(snip)

If your intent is to drive directly from the uP, you may want to
consider how the load switching will effect the uP. You will probably
get ground bounce. In addition, as you increase VGS, there will be
current flow from CDG. If the drain voltage is falling like a rock, it
will generate current that opposes your gate drive. What I'm leading
to here is you should probably buffer the uP from the power fet.

I just finished looking into various MOSFET gate drivers for my design.

(snip)

I also played around with a homebrew MOSFET driver using an NPN and PNP
transistor, and a few resistors and diodes, and it seemed to work pretty
well in the simulator. I also set it up with a bootstrap to the MOSFET
drain, with the idea that maybe a driver could be built into a MOSFET,
but
it's probably better to tie the voltage supply for the driver to a 5 volt
or 12 volt supply. So you can omit some of this circuitry, but it is
probably a good idea to have some sort of limiting resistor. I tried a
simpler driver with an NPN and PNP with bases tied together as the input
and emitters tied together as the output, with collectors across a 12
volt
supply, and somehow there was simultaneous conduction and one of the
transistors popped.> Paul


Did you use a resistors in each base, or just tie them together?



I just tied them together. It's basically two emitter followers. They
should never be both on at the same time, but if one is slower than the
other, I guess it can happen, and did. The simulation looked OK.

Paul


.

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