Re: sport rocket staging timer

John Fields <jfields@xxxxxxxxxxxxxxxxxxxxx> wrote in
news:3jde14lutf2khpi3hacnqudiue3bs6adi2@xxxxxxx:

On Tue, 29 Apr 2008 08:20:12 GMT, Smaug Ichorfang <sm@xxxxxxxxxx>
wrote:
Thanks! I'll give this consideration!

Some friends would like to build a down-sized model of a two-stage
sounding rocket. I'm trying to come up with a design for a timer to
ignite the second stage. The timer should be triggered by a "g"
switch which marks first stage ignition, and time out after (an
adjustable) 1.5-2 seconds, just after the first stage burns out.
Commercial designs are available for around $90. I only need to build
ONE of these andd don't have the programmer so a pic or BASIC STAMP
are out. Any ideas or schematics for an analog or simple digital
timer for this application?

---
View in Courier:


Vcc>-+---------+-----+---+------+--------+
| | | | 8| |
[10K] [10K] [1M]<-+ +---+---+ [100K]
| | Rt| 2|_ Vcc _|4 |
+-[100nF]-+-----|-----O|T R|O---+
| | 6| | |
+ +------|TH 7555| [100nF]
| | 7|_ |3 |
| O +-----O|D OUT|O---|--->OUT
| O +| | GND | |
| [3.3µF] +---+---+ |
| Ct| 1| |
GND>-+---------------+----------+--------+


T = 1.4 Rt Ct

JF


.

Relevant Pages

  • Re: Lahman, how ya doing?
    ... One also has to be careful about books with 'UML' or a specific OOPL in the title; they are good at describing how to express your design in the UML or OOPL syntax but they tend to be short on advice about coming up with a good design in the first place. ... The author has made clear in an early chapter that the book is about OOA, and what UML is introduced will serve that purpose. ... When we talked about things like hardware propagation delays before you didn't seem to think they were relevant (i.e., all the controller processing could be completed in a base clock tick interval (100 ms) in the real controller). ... But speaking of maintainability, if it were to be used in a real-time system with Timer reading the system clock rather than incrementing a counter, could it easily accomodate that? ...
    (comp.object)
  • sport rocket staging timer
    ... I'm trying to come up with a design for a timer to ignite the ... just after the first stage burns out. ...
    (sci.electronics.design)
  • Re: Strange Behavior
    ... design issues in this version. ... As to the Queue issue & searching it, there is only one server this is ... not tossing another timer at the problem. ... Thread creation is something that should take ...
    (microsoft.public.vc.mfc)
  • Re: System Generator pcore I/O performance results
    ... dividing timer result by 8 --> ... and "get" operations for transferring data over FSL. ... I'm not implementing cache with this design. ... created the pcore suggest to remove this line in the xparameters.h ...
    (comp.arch.fpga)
  • Re: Synthesisable Timer in VHDL
    ... i am currently working on a "toy" design of my first big project (in ... VHDL) on the Xilinx Spartan III starter kit. ... way of implement the timer in VHDL? ... clock period of your clock and the time period for your delays. ...
    (comp.arch.fpga)