Re: Digital wireless systems



On May 15, 10:33 am, john <conphil...@xxxxxxxxxxx> wrote:
Hi,

I am looking for a digital design or technique that I can use to
transmit the 48bit of data at 1.5MHz frequncy wirelessly. So, what I
gathered so far is that a digital frequncy modulator can be made using
a FPGA and the demodulator can also be made using FPGA. Am I right ,
if yes then i need more guidance , some literature to understand
exaclty how can I do this? The thing that I do not still understand
that If I am right about the FPGA based frequency modulator and
domodulator then how would I design the wireless part of the system?

John

After re-reading some of your posts, it seems clear that your data
rate is 72 Mbps. It would help to know if this is a one-off
(feasibility) or a design project ... Since you already have a Spartan
on the transmit side, you can use it as a modulator (e.g QAM),
followed by an up-converter, and use another FPGA after down-
conversion on the receive side. I think questions about what "chips"
to use for the RF (or optical) section might be more productive after
we know more about the cost / size and power constraints.

Frank Raffaeli
.



Relevant Pages

  • Re: stimulus for FPGA
    ... If you are new to FPGA, probably new to VHDL and Digital Design. ...
    (comp.arch.fpga)
  • Re: Digital wireless systems
    ... I am looking for a digital design or technique that I can use to ... transmit the 48bit of data at 1.5MHz frequncy wirelessly. ... a 1.5Mhz carrier frequency to send 48bits. ... a FPGA and the demodulator can also be made using FPGA. ...
    (sci.electronics.design)
  • Re: Digital wireless systems
    ... I am looking for a digital design or technique that I can use to ... transmit the 48bit of data at 1.5MHz frequncy wirelessly. ... gathered so far is that a digital frequncy modulator can be made using ... a FPGA and the demodulator can also be made using FPGA. ...
    (sci.electronics.design)
  • Re: Series Termination
    ... reduced the trace width necessary for a particular transmission line. ... So far there is no useful output from the FPGA, ... much design there yet) and transmitted. ... loops with multiple caps on the supply lines. ...
    (sci.electronics.design)
  • Re: How big is my vhdl and am I approaching some size limitation on the chip.
    ... put you off going for FPGA. ... The Virtex range is ... ERROR:Cpld:1063 - Design requires at least 947 macrocells, ...
    (comp.arch.fpga)

Quantcast