Re: Alumina Substrate
- From: John Larkin <jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx>
- Date: Thu, 05 Jun 2008 13:41:58 -0700
On Thu, 05 Jun 2008 20:18:48 GMT, Rich Grise <rich@xxxxxxxxxxx> wrote:
On Wed, 04 Jun 2008 12:46:27 -0700, John Larkin wrote:
We have trouble keeping impedances reasonable on 8-layer boards with
Er=4.6.
Forgive the dumb question, but what's "Er"?
Dielectric constant, relative to vacuum. FR-4 runs about 4.6, which is
about 15 pF per square inch of 0.062 board, side-to-side. That makes a
50 ohm microstrip (surface) trace about 120 mils wide.
Make the dielectric thinner, and capacitance goes up, so a 50 ohm
trace has to get skinnier. Sandwich the trace inside between planes,
and you have stripline, even lower impedance. At 8 or so layers,
inner-layer traces start to get too skinny to have reasonable
impedances. 100 layers of ceramic, with Er=10 maybe, boggle my tiny
mind.
John
.
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