Re: PLL frequency multiplier.

Joerg wrote:

But the real Frank Buss method would be to pipe that 400Hz into a uC and
run a timer in there. A software loop would keep adjusting the timer's
overflow register until the timer does exactly 96 rollovers per 400Hz
cycle. Then use that timer overflow signal to toggle a port pin which
will now deliver exactly 19.2kHz at 50% duty cycle. This method should
require the least in parts. Heck, the uC doesn't even need a stable
clock, it can run off its on-chip RC oscillator. Best case it'll be two
components, the uC itself and a 0.1uF bypass cap.

It depends on the accuracy requirements. If I use a cheap PIC with 4 MHz
internal clock, I would need some machine cycles (4 MHz PICs runs with one
million instructions per second) to toggle the pin. Would need considerably
work to balance the code paths for the same time and even then there would
be a jitter of about 2% (19.2 kHz / 1 MHz * 100), and worse when I need to
adjust it up/down by one. I assume the CD4046 is more accurate.

--
Frank Buss, fb@xxxxxxxxxxxxx
http://www.frank-buss.de, http://www.it4-systems.de
.

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