Re: Ever heard of Potato Semiconductor?

On Sun, 06 Jul 2008 12:16:03 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@xxxxxxxxxxxxxxx> wrote:


On Sun, 06 Jul 2008 11:42:09 -0700, John Larkin
<jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:

On Sun, 06 Jul 2008 11:28:23 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@xxxxxxxxxxxxxxx> wrote:


On Sun, 06 Jul 2008 10:35:07 -0700, John Larkin
<jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:

[snip]

One problem with running CMOS at high speeds is power consumption.
They don't mention this in any usable form.

Fabless...

Potato Semiconductor Corporation is a private fabless IC design house
which locates in San Jose, California.

In and Out via CMOS, probably CML or PECL inside...

Why ecl inside? CMOS logic can already get down to sub-100 ps logic
functions "inside", as is common in fpga's and high-end processors.
The speed problem is i/o.



By applying our powerful industry-leading technology in IO interface,
logic cells & special design rule, we can design most of existing
chips with higher frequency, higher performance, higher reliability,
and less noise.

I've seen no patents assigned to Potato, or to their guru, Richard
Kao.



Their English is atrocious.

John



Taiwan

Design center is in San Jose. Fab is said to be by TSMC. They may be
real, but the specs are dicey.

John



Pico-second speeds in CMOS are power hogs... my usual design
cross-over point is around 250-300MHz.

In a WiFi repeater chip I come from 5GHz down to 250MHz in CML, then
CMOS.

...Jim Thompson

FPGAs manage a million gates at 600 MHz or so. Some of the cmos LVDS
parts run at a couple of GHz. It deosn't seem like simple gates and
flops would be a power problem in cmos.

John

.

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