Re: Creating Thermal Vias?
On Wed, 6 Aug 2008 10:29:46 -0700 (PDT), Pavan R Nyama
<pavan.nyama@xxxxxxxxx> wrote:
Hi,
I have a board with a copper pour on both the top and bottom layers,
and i want to place a via for thermal reasons. However, i dont want to
have the ring of no copper around the via - i essentially want to
create a plated hole straight through the board without changing
anything else on either layer. Does anyone have any suggestions on how
to do this?
Im using Altium 6, so application specific help would be even more
appreciated :)
Asign both copper pours to the same netlist node.
Remove any thermal relief from the pth's or via's selected pattern.
RL
.
Relevant Pages
- Re: Creating Thermal Vias?
... I have a board with a copper pour on both the top and bottom layers, ... and i want to place a via for thermal reasons. ... the pad definition. ...
(sci.electronics.design) - Re: Creating Thermal Vias?
... I have a board with a copper pour on both the top and bottom layers, ... and i want to place a via for thermal reasons. ... reason to use thermals any more. ...
(sci.electronics.design) - Creating Thermal Vias?
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(sci.electronics.design) - Re: Utility of copper pours on four-layer boards
... flooding the top and bottom layers of a four layer boards (where the inner layers are power and ground) comes from. ... I'm often having to get our techs to widen the clearance between the copper pours and controlled impedance traces because they like to set the clearance from the copper pour to the other signal nets so tightly that they end up turning microstrip lines into coplanar waveguides and significantly altering their impedances. ... It occurred to me that rather than continually dealing with this, it might be easier to just tell them not to use a copper pour on the top or bottom layers at all since I can't think of any particularly compelling reasons to do so in the first place. ...
(sci.electronics.design) - Re: Utility of copper pours on four-layer boards
... top and bottom layers of a four layer boards (where the inner layers are power and ground) comes from. ... I'm often having to get our techs to widen the clearance between the copper pours and controlled impedance traces because they like to set the clearance from the copper pour to the other signal nets so tightly that they end up turning microstrip lines into coplanar waveguides and significantly altering their impedances. ... copper pour on the top or bottom layers at all since I can't think of any particularly compelling reasons to do so in the first place. ...
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