Re: Blast from the past... Z80!

In article <47e3a336-6e35-4219-986e-716c203d95d9
@w39g2000prb.googlegroups.com>, kensmith@xxxxxxxxx says...>
On Jan 30, 8:39 pm, "langw...@xxxxxxx" <langw...@xxxxxxx> wrote:
On 31 Jan., 02:48, krw <k...@xxxxxxxxxxxxxxxxx> wrote:



On 31 Jan 2009 00:27:13 GMT, Jasen Betts <ja...@xxxxxxxxxx> wrote:

On 2009-01-30, krw <k...@xxxxxxxxxxxxx> wrote:
In article <glvoah$3u...@xxxxxxxxxxxxxxx>,
pNaonStpealm...@xxxxxxxxx says...>
On a sunny day (Fri, 30 Jan 2009 12:57:20 -0600) it happened krw
<k...@xxxxxxxxxxxxx> wrote in <MPG.23ed098862221bb4989...@xxxxxxxxxxxxxxxxxxx>:

In article <glveve$im...@xxxxxxxxxxxxxxx>,
pNaonStpealm...@xxxxxxxxx says...>
On a sunny day (Fri, 30 Jan 2009 07:18:08 -0800) it happened John Larkin
<jjlar...@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote in
<5c66o4l4nlknnavh33tmc20had460i8...@xxxxxxx>:

On Fri, 30 Jan 2009 06:48:06 -0800 (PST), MooseFET
<kensm...@xxxxxxxxx> wrote:
I like the Z80 and 8051.  They are very nice processors.

YUK!

No wonder you hate programming.
You simply never programmed a good processor.

The Z80 is a very very very nice processor to work with.

If you enjoy moving data from here to there and back.  I'm with
John.  Yuck.

Sorry I do not get that.
Would you care to elaborate on 'moving data from here to there'?

95% of the instructions are moves (load/store register).

closer to 40%

Two loads, op, store.  Ok, 75%.  It was still a PITA.  That's why I
liked the 8051.  Besides the neat peripherals, there were so many
places to get data from without moves.  The instruction set is kinky
though.  Of course RISC pretty much solves the excessive load/store
issues and kinky instruction sets.

RISC operates on registers, so anything to do with memory will
will have to be done with a load and/or a store

But there are a bazillion registers so percentage of load/store
instructions in a code stream drop like a stone.

RISC means Reduced Instruction Set Computer.

Reduced Instruction Set Complexity. A modern RISC computer has just
as many, if not more (depending on how you count), instructions
than a modern CISC.

It really doesn't say which ones get taken out.

Yes it does. He's right. Load/store ops get separated from ALU
ops and RMW ops are unheard of. That is the *key* difference
between RISC and CISC.

Ideally they are faster because they
implement the low number of instructions very efficiently.

Absolutely wrong.

There is
no law that says that a very awful machine can't be made as a RISC.

There is no law that says that a very awful machine can't be made
of CISC (oh, wait). The difference is that we have an example of a
commercially successful CISC that is truly awful. No such example
exists of a RISC.


.

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