Re: STP24DP05


"nospam" <nospam@xxxxxxxxxxxxxx> wrote in message
news:5mjbo4te1g89hjl47u3dop4i5kr8of65g5@xxxxxxxxxx
"BobW" <nimby_GIMME_SOME_SPAM@xxxxxxxxxxxxxx> wrote:

You must ABSOLUTELY use a clock distribution chip with proper termination
on
each clock line.

No you don't. Clock skew is only relevant between adjacent sections of the
extended shift register. The data *** is pretty lousy but it looks like
worst case @ 5v the part can accommodate up to 4ns of clock skew between
adjacent chips (9ns min prop delay less 5ns recommended hold time).

Much easier to use a single clock.

The maximum number of devices in the chain is limited by clock loading
slowing the edges with the potential to introduce skew. No reason why
clock
buffers could not be inserted in the chain prodding you can insert an
adequately matched delay in the data at the same place.

If you are interested in the error status coming out of the shift register
you will obviously have to look at it with respect to a clock from the end
of the chain.
--

The issue is signal integrity. You have to have a clock with monotonic edges
and one that doesn't violate undershoot/overshoot specs.

It used to be, with slow clock edges, that you could connect a single clock
source via daisy chain or star configuration. That just isn't true any more.

I inherited a design that used a single clock driver output to connect to
several pins. Although the clock rate was slow (1MHz) the rise/fall time was
about 1ns. This resulted in double clocking due to the placement of the
reflection at one of the pins. It failed to pass error free data.

You can't use source termination for multiple if multiple clock pins are
connected in a daisy chain when the receivers are LVTTL or CMOS logic levels
because you won't meet their levels during the forward transmission of the
edge (and then comes along the reflected wave to add insult to injury). You
have a chance using source termination in a star topology but it's kinda
tricky.

If you use end termination for the daisy chain and star configuration then
you have to have a super low impedance clock driver to assure that it will
launch a full amplitude wave into the trace(s). Otherwise, you won't meet
the logic levels.

It is MUCH easier to bite the bullet and put in a clock distribution chip.
They're cheap and they work and they allow you to sleep peacefully.

Bob
--
== All google group posts are automatically deleted due to spam ==


.

Quantcast