Re: Series Termination

I missed two points in my post:

It is a BPSK transmitter.

With a 10 MHz input I couldn't figure out how to get a 1.023 Mhz clock
using only the FPGA PLLs. So, when I get to that point if I still
can't figure out how to generate the clock I'll either add an external
PLL or eliminate the requirement. The code sequence length is 1023
chips and it would be nice if the code repeated every ms, but that's
not necessary.

Thanks again!
.