Re: Hardening a simple op-amp circuit against EMI
- From: Joerg <notthisjoergsch@xxxxxxxxxxxxxxxxxxxxx>
- Date: Tue, 17 Mar 2009 11:36:09 -0700
D from BC wrote:
On Tue, 17 Mar 2009 08:52:33 -0700 (PDT), Russell Warren
<russandheather@xxxxxxxxx> wrote:
I've got a simple op-amp circuit that is misbehaving in an EMI
environment. It looks like below (hopefully the ascii drawings work
out)...
___10k_______
| |
GND--------|\ 20k
| \____|___
--100----------|+/
|/
The numbers are resistor values and the + input comes from a unity
gain buffer.
On first inspection my first obvious thought was to limit the
bandwidth to avoid EMI issues (circuit only actually needs kHz'ish
bandwidth) so I put a simple RC filter on the input as follows:
___10k_______
| |
GND--------|\ 20k
| \____|___
--100----------|+/
| |/
1u =
|
GND
But this still had EMI issues and was probably bad because hanging a 1
uF cap off the input is a bad idea? Not that I have any fundamental
basis for making that statement.
Consulting an EMC design book which has been *extremely* helpful in
the past (EMC for Product Designers by Tim Williams), one of the
things it recommends is putting low value resistors at each of the
inputs, right at the pins. It also indicates that the values should
be no larger than a few hundred Ohms. ie: adding 200 Ohms to each pin
of the circuit above:
___10k_______
| |
GND----200-|\ 20k
| \____|___
--100------200-|+/
| |/
1u =
|
GND
I'd like to understand what is going on here. My questions are:
1. Is hanging a large capacitance on the input of an op-amp a bad
idea? If so, why? I saw some rumblings somewhere about CMRR issues,
but don't get it.
2. With the op-amp having a high input impedance, what is the reason
for limiting the resistors at the input pins to "up to a few hundred
Ohms"?
I'm trying to simulate the impact of it all in Switchercad, but I'm a
hack and my attempts have not been that illuminating. I've spent some
time trying to work out how to simulate and understand when an
amplifier circuit is stable or not, but haven't been able to fully
grasp phase margin and certainly not how to simulate it properly.
Any help is much appreciated! I have an extreme dislike for doing
anything because "that's just how you do it" and want to understand
what is going on underneath.
Russ
Is is conducted noise, capacitively coupled noise, RF pickup noise or
magnetic induction noise?
Ok, Russell, I won't be able to see your posts and replies because you use gmail (maybe use a better address?). But I want to alert you to something that is rarely known in the trade:
Opamps with bipolar transistors in the input can cause RF to be rectified. A cell phone transmitting in the GHz range can cause that trouble even with an opamp that has only 10MHz or so GBW. This is because the BE junctions at IN+ and IN- rectify RF and that rectified signal shows up in your signal. With GSM you'd have pretty hard "rat-tat-tat" style bursts when the phone connects to a new tower or checks in once in a while. CMOS opamps suffer much less from this behavior because there is no BE junction that is slightly conducting, there are usually only substrate diodes that are sufficiently reverse biased (as long as your input swings stay withing the rails).
With strong EMI none of the external methods such as ferrite beads and capacitors help much. I had one such case where the EMI went straight through the SO-8 plastic smack dab into the chip. So I recommended a CMOS opamp to that client or, as an alternative, shielding. We then tried both and both fixed it. Since they really liked the BJT-based amp for audio noise level reasons they opted for shielding.
--
Regards, Joerg
http://www.analogconsultants.com/
"gmail" domain blocked because of excessive spam.
Use another domain or send PM.
.
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