Re: MOSFET breakdown prevention in a boost converter

On Wed, 1 Apr 2009 12:52:19 +0100, "Holloway,Graham \(UK\)"
<graham.holloway@xxxxxxx> wrote:


<adeivw@xxxxxxxxxxxxxx> wrote in message
news:572f9e25-8f37-463a-935a-104ee97ef57f@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Hello:

I am designing a boost converter, and I am uncertain whether I need to
take specific measures (and which) to protect the main switch MOSFET
from the drain-source voltage breakdown. The fet is incorporated in
the switcher IC, and has the maximum voltage rating of 60V. I want the
converter's output voltage about 55V. Now, if one takes into account
the parasitic inductance of the PCB tracks and of the switcher's
package wires, one would conclude that high-voltage (albeit very
short) spikes, well above 60V, would be produced across the fet's
drain-source at switch-off. Even if I could somehow clamp the D-S
voltage at the switcher's connection to the PCB board, there would
still be considerable spikes due to the package's own wires (it is a
TO220-5).

Can someone help and tell whether I should bother about these spikes,
and if yes - to which extent? Many thanks!

-- A

Put a tap in the inductor not far from the output. This will reduce the
voltage swing on the MOSFET, but increase the current slightly. Bear in mind
that the breakdown voltage often has a negative temperature coefficient.

Graham H

Actually Vds limits for discrete mosfets increase with higher
temperature but there are very few app environments that can benefit
from this feature. Discrete mosfet voltage breakdown is not
catastrophic, only energy-limited (as per TVS-characterized zeners)
and moisy. The self-heating characteristic of this breakdown limit can
even be self-regulating at really low temperatures.

Integrated mos structures may show the limit characteristics of the
host structure, however, where breakdown behavior is not so
predictable. By reducing layout loop area, adding current-snubbing and
using rectifiers with low forward overvoltage (schottkys), you should
be able to approach paper limits in boost converters, if transient
response (start-up and transient output voltage overshoot) is
well-controlled. Larger than nominal output capacitance may help.

Some power integrated circuits display a odd behavior in the presence
of a range of dv/dt or di/dt values - you should make enquiries with
the device mfr about any unexplained behavior. There may be a simple
empirical solution, whether or not the mechanism is fully understood,
or whether an explanation is forthcoming.

RL
.

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