Re: Overview Of New Intel Core i7(Nehalem) Processor

On Sun, 14 Jun 2009 21:56:54 -0700, John Larkin
<jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:

On Sun, 14 Jun 2009 21:32:47 -0700,
"JosephKK"<quiettechblue@xxxxxxxxx> wrote:

On Sun, 14 Jun 2009 21:43:05 +0100, Nobody <nobody@xxxxxxxxxxx> wrote:

On Sun, 14 Jun 2009 11:33:29 -0700, JosephKK wrote:

But you shouldn't need to write parallel code. You should be able to
specify the problem and let the compiler take care of the details.

This is starting to matter. Multiple cores are the norm even on desktop
systems now, and the trend is towards even more cores. Forcing the
programmer to partition the task manually is both fragile and costly.

Have a blast with your idea. Write the compiler. Warning, the
underlying hardware is usually strictly von Neumann procedural.

Actually, modern hardware shares some similarities with lazy evaluation
(used by most Haskell implementations), but it hides most of this to
provide compatibility with the imperative model.

BRRRRRRRRRTTTTT
You are showing arrogant ignorance. Every X86 is on the imperative
von Neumann model. For that matter so are every uP that i have heard
of, such as: 6500, 6800, 68000, MIPS, SPARC, HP-PA-RISC, 805X, 804X,
PIC, AVR, ACORN, ARM, Transputer, MicroNova, MicroVAX, Alpha, Itanium,
PPC and others for sure. So are many mainframes like IBM s/360,
s/370, s/390, Crays, CDC Cybers, DEC 10s and many more. Not all of
these are still made. Yet every one at the machine level is
imperative procedural hardware. Nor does it matter what user language
interface is used, the hardware is the same.

Lots of machines actually do out-of-order execution, but it's
(usually) not visible in computed results.

http://en.wikipedia.org/wiki/Out-of-order_execution

John

A little reordering on the fly does not change the instructions from
imperative to declarative, every one is a "machine do this" command.
.

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