Re: Can I route a PCI Clock line longer than 2ns?



"krw" <krw@xxxxxxxxxxxxxxxxx> wrote in message
news:1lio35h5e96t0l1tib6v000f773d3epdim@xxxxxxxxxx
On Sat, 20 Jun 2009 01:14:10 GMT, Jon Kirwan
<jonk@xxxxxxxxxxxxxxxxxxx> wrote:

On Fri, 19 Jun 2009 20:04:24 -0500, krw <krw@xxxxxxxxxxxxxxxxx> wrote:

On Sat, 20 Jun 2009 00:46:35 GMT, Jon Kirwan
<jonk@xxxxxxxxxxxxxxxxxxx> wrote:

On Fri, 19 Jun 2009 19:04:17 -0500, krw <krw@xxxxxxxxxxxxxxxxx>
wrote:

On Fri, 19 Jun 2009 21:06:48 GMT, Jon Kirwan
<jonk@xxxxxxxxxxxxxxxxxxx> wrote:

On Fri, 19 Jun 2009 21:01:18 GMT, nico@xxxxxxxxxxx (Nico Coesel)
wrote:

Devlin <springzzz@xxxxxxxxx> wrote:

I am designing a system which is consdering using PCI as
backplane
bus, which has six slot and 3 inches between each. I Can't
decide If

That won't work. You'll need a PCI-PCI bridge to get more than 4
slots. The spec says 4 slots is the maximum you can have on a PCI
bus.

I vaguely recall the spec specifying pF loads. Something like
100pF
total. Memory serving, they mention that there is 10pF reserved
for
each board, 10pF for each connector. With a chipset on one side
and a
bridge on the other (each also with 10pF) that leaves 80pF total.
At
20pF per inserted card (board and connector), this is 4 slots.
But I
seem to recall the classroom teacher telling us also that if you
can
use low-pF connectors it is possible to push things a little.
You'd
still have to assume 10pF for each inserted card and 10pF for each
end, so that is 80pF for six cards, without the connectors added
in.
Leaving 20pF/6 or about 3pF per connector. Not sure if that is
possible, but if my memory from the classroom remains correct,
then
that just _may_ be possible to find.

The spec gives examples based on "loads", where an add-in card is
two
"loads" and an integrated device is one "load", with a maximum of
ten
"loads".

I think they told me that a "load" was 10pF. I forgot to mention
that
if there is no bridge load, that's another 10pF added up. So 6
slots
may leave 30pF/6 or 5pF per connector, if there is only one chipset
side and no bridge (and allowing 10pF for the chipset itself, which
may or may not be correct for it.)

It is just an example though. The designer has to do the
analysis.

My recollection is that the pF loading _was_ the spec to analyze
towards. The 100pF total was for 33MHz, memory serving. I think
that
went down to 50pF for 66MHz. (Do they specify things in terms of
current, now, rather than pF loading?)

Nope. It's not in there. There are signal integrity and timing
requirements, nothing about "loads", "pFs", or "ins". I should look
to see if I still have a spec on a disk somewhere (no one really uses
PCI anymore).

I see. You mean, for example, like the clock line skew spec of 2ns
for 33MHz and 1ns for 66MHz.

Pretty much, though that doesn't cover the signal integrity part very
well. ;-)

Everything eSATA now, eh?

PCIe

PCIe is much easier.
I recall 11 or 12 inches max for PCI. You have to figure out what the
return time is for the bus, including connector capacitances and such.
It?s a reflected wave bus, the last card is the first to get switched.
Here an old edn article. Tprop (round trip) must be 10ns.
http://www.edn.com/archives/1994/112394/24df3.htm

Cheers


.

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