Re: Advice on PC Based Logic Analyzer
- From: Rich Webb <bbew.ar@xxxxxxxxxxxxxxxxxx>
- Date: Tue, 15 Apr 2008 09:19:24 -0400
On Tue, 15 Apr 2008 02:15:21 -0700 (PDT), logicgeek
<logic.analyzer@xxxxxxxxxxx> wrote:
What I like about the Annie-USB is that it comes complete with SMD
grabber clips that optionally would cost some extra money.
If you have the time go to www.janatek.com/annie-usb_main.htm. It
retails just below $500..My only concern thou is that it sports only 8-
channels. However they have a nice little article on their website
about evaluating logic analyzers and I must say that I agree with this
article in that I will rather buy 8 'good channels' with sufficient
buffer depth than 32 channels and anyway not be able to use them all.
Eight are useful, 16 are better, and 32 (or more!) are occasionally
necessary. Like many things in life: "It depends."
The traditional need for 32 channels would be a 16-bit address bus,
8-bit data bus (or 8 A + 8 D + 8 A/D shared), plus a handful of
control lines. That enables one to trace a program's flow of
instruction and data fetches, jumps, etc. Typically one would trigger
on a specific instruction-fetch address and then examine the following
behavior. This kind of analyzer often came, or could be provided, with
the ability to interpret and display the assembler equivalents for the
captured data.
In the microcontroller world, however, generally the address and data
busses are contained within the processor core, so the analyzer is
relegated to watching the general-purpose I/O lines and the ports used
by peripherals. Much of the time, eight is indeed enough. But, if one
is managing operations on a chip with multiple 8-bit ports and a
handful of serial peripherals, one runs out of probes pretty quickly.
The faq article is at: http://www.janatek.com/faq_buying_logic_analyzer.html#6
I've talked to some people and most of them said that I should opt for
sufficient buffer depth. What is the feedback of those happy okes
using logicport?
Consider that a 1 Mbit buffer will be filled by a 10 Msps clock in
only 100 msec. If everything being examined by the analyzer is in the
same time scale, that may not be a problem but that 1 Mbit could turn
out to be far too short to look at fast events that are separated in
time.
A smaller buffer that incorporates transitional sampling does a great
job in capturing narrow but widely separated events. I usually sample
at 100 MHz and can easily look at related events separated by hundreds
of msecs (or longer).
There are times (no pun intended...) when there's a "lot going on" and
simply triggering on the easy target, e.g., first rising edge, would
fill the buffer before the event of interest. In that case, all that's
needed is to delay the trigger based on an edge count or time.
--
Rich Webb Norfolk, VA
.
- References:
- Advice on PC Based Logic Analyzer
- From: logicgeek
- Re: Advice on PC Based Logic Analyzer
- From: Jean-Yves
- Re: Advice on PC Based Logic Analyzer
- From: logicgeek
- Advice on PC Based Logic Analyzer
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