Re: ringing with mosfets problems

In article <42de9f8a$0$6470$cc9e4d1f@xxxxxxxxxxxxxxxxxxxxxxxx>,
exxos <exxos@xxxxxxxxxx> wrote:

> Its hard to say, it looks like there are 2 spikes on the supply
> rail, though when you have a 50:50 duty cycle you can't see
> them, but at 50:30 you get something like a 1V spike which is
> bad. I didnt notice that until just. Even though the wave looks
> a bit crappy, the waveform does not change much, but the supply
> does.... it looks like a supply problem now, so I will do was I
> was thinking yesterday and used seperate regulators. That makes 6
> of them in total.. a lot of fun....

Have you considered doing a Spice simulation of your
circuit? 6 months ago I had a job to redesign a 10A
PWM'd generator field-coil driver, where the original
kept blowing up it's output power darlingtons.

I LTspice'd the original, and at first glance it looked
all right... Ok, the output transistors did run slightly
hot at 10A, but not outrageously so. Then I added-in
reasonable values for the supply cabling, etc, just 10-100
milliohms or so.

In the simulation, at about 5Adc output something nasty
started to happen. The output ON pulse first acquired
a small notch in it. Just a few mA higher it became an
actual double pulse, and a few mA above that the whole
thing locked up, output transistors motorboating, out
of control, huge dissipation, probable meltdown.

Fortunately I had some oscilloscope photographs of a
running system and, sure enough, signs of that notch
were present on one photograph, at about 6Adc output.
So this gave confidence in the LTspice simulation.

Probing around the rest of the simulation showed that
an earlier stage was being unexpectedly modulated by
the power supply ripple, with the modulation reaching
a peak effect about 2/3 into each ON period. At higher
output currents that local positive feedback loop took
over.

LTspice indicated that the problem could be cured with
an impractical number of low ESR capacitors on the
main supply rail. But also showed that the far easier
solution was to simply improve the decoupling on the
sensitive stage.

No breadboarding, the redesigned circuit went straight
to pcb layout, and worked ok first time.... *cough*,
well nearly first time, but we don't mention that perp
because no re-layout was required. :)

Intelligent simulation can be a very a useful design tool.

--
Tony Williams.
.

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