Re: Monostable made from OR gate and CR network , pulse duration ??

On Nov 22, 5:35 am, "Arfa Daily" <arfa.da...@xxxxxxxxxxxx> wrote:
"Franc Zabkar" <fzab...@xxxxxxxxxxxxxxxxx> wrote in message

news:67afi49p8mtifo6frjjbas401k183n9q5q@xxxxxxxxxx





On Sat, 22 Nov 2008 02:28:57 -0000, "Arfa Daily"
<arfa.da...@xxxxxxxxxxxx> put finger to keyboard and composed:

Just a suggestion, but wouldn't it be a whole hell of a lot simpler to
just
use a 555 timer IC ? Just the chip, two Rs and one C (two Cs if you want
to
be pedantic and decouple the control pin) to make a monostable which will
give utterly predictable results over a wide supply voltage and
temperature
range, and has a very simple timing formula of approx 0.7CR.

Arfa

Another option would be a 74LS123. Perhaps the OP's application
doesn't require precision, and perhaps he has a spare gate.

- Franc Zabkar

Granted. But as you say, the actual thresholds on TTL can vary widely from
family to family, which may give a huge discrepancy betwen the figure you
think you should get, and what you really do get. OK I suppose if it's just
something for yourself, but could cause problems if you were going to do a
few of them.

I was thinking also, that the circuit the OP is describing is in fact just a
(power on ??) delay with a buffer gate on the end, as there doesn't seem to
be any mechanism to reset the timing network after the initial pulse. Unless
of course, the OP's "common starting point" is in fact switched between rail
and ground. You sometimes used to see tricks like this on older logic
boards, to provide a delayed reset to other bits of circuitry such as a CPU
IC. These days, they tend to use dedicated reset ICs, which again, give
predictable and repeatable results.

Arfa- Hide quoted text -

- Show quoted text -

Ok ... Well this birds nest is about 35 years old , your right on the
'tricks' bit , there is more than one set of discreat 'cr's' on the
board ,

I did the same calculation , with the long 'cr' time the vlaues given
may be attached to the device thats making a 0.125 uS pulse (measured
on teck-t 500 mhz dig scope)

CR = approx 62% full charge voltage, (5 volts) so i assume the devices
are toggeling at the zero to logic 1 transission voltage of the
chip ...which is less than 50% rail .... so its going over early ...

Ive not seen any guide lines on expected pulse duration from this
arrangement , 125 nano seconds is quite sharp even for the new
devices .... looks like , may be the only way is to remove the C ,
R , components , measure them and if in tolerance then assume that
what is measured is correct .... I could look at the charging curve
to see when it chnages state .. and work backwards ?

tnx - G ..



.

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