Re: Deep Zoom on Mandelbrot set

[Please do not mail me a copy of your followup]

=?ISO-8859-1?Q?Manuel_H=F6l=DF?= <manu@xxxxxxxxx> spake the secret code
<dmihqa$1hp$1@xxxxxxxxx> thusly:

>To be honest: Before your post I was not aware of FPGAs at all and what
>exactly they are.

FPGAs are pretty cool. You get a very flexible design process -- and
frankly "designing" the hardware is more like writing a program if you
work in VHDL or Verilog design languages. So its very accessible to
the average software developer. Implementing a circuit in an FPGA is
not as fast as implementing your own custom circuit from scratch in a
traditional VLSI design, but sine the FPGA is reprogrammable, its very
easy to iterate the development through to a finished working design.

>I've now looked a bit on the web and it indeed looks
>quite interesting for special numeric algorithms like in our case. At
>the moment I have not the time to do it but I think later I'll try to
>learn mor about this.

You may want to look at hardware or peripherals that support
"reconfigurable computing". This is the idea of having a peripheral
card that plugs into the PC (or some other host) and contains FPGA
devices for custom circuitry. The FPGA hardware is then used as a
special purpose accelerator for whatever application happens to be
running. Appliation A loads its configuraiton of the FPGA and
application B loads its configuration of the FPGA. Each application
gets what looks like a special purpose accelerator through the same
general purpose piece of hardware.

So far, this idea hasn't caught on to the general computing population
because whenever a need is identified for accelerators that have broad
appeal they get incorporated as traditional VLSI: graphics processors
and sound processors are examples of this.

>Your page has some information about the Xport 2.0 Features.

(Note: its not my page, its the page of the vendor that makes the
Xport 2.0 card. This is really just a small card that attaches to a
GameBoy Advance containing a Spartan II FPGA chip from Xilinx. You
can get Xilinx evaluation boards directly from Xilinx's web site
<http://www.xilinx.com>. They have a free set of tools for writing
circuit designs as VHDL or Verilog and compiling them into a
downloadable configuration for the FPGA chip.

>What would
>still be interesting in order to get a feeling for the possibilities in
>performance would be a typical clockrate for a FPGA. Having the
>possibility to do operations with a big mantissa roughly in the same
>speed as the X86-FPU does for 64-bit would be great. But even if it's
>some factor slower it might be a lot faster than a bignum-implementation
>on the PC.

Yeah, if you're working on word-sizes that are comparable to the word
size of a native x86 architecture, then you're going to have to do
quite a bit of work to exceed the floating-point performance of the
x86, at least for modern versions of the architecture at modern clock
speeds. However, you can take shortcuts when you know the exact
computation you need to perform. For instance, for M-set plotting you
can compute subterms that are needed to compute z^2 and re-use them to
compute the |z| bailout test. You can also do things like build a
block to compute the M-set iteration and then replicate that block
until the FPGA is filled allowing you to compute multiple orbits in
parallel.

I targetted deep zoom as that is the place where you see the plotting
performance of the M-set drop through the floor on a typical PC. As
long as the coordinates are within the range of an IEEE float or Intel
80-bit float, then the x86 CPU chugs through that pretty fast. As
soon as you zoom in to where the 80-bit float doesn't have enough
dynamic range and you have to drop down to a bignum implementation
then things start crawling. An additional factor is that the bignum
is typcially fixed-point and not floating-point.

There is also the problem of the "winodw of opportunity". This comes
up in hardware design all the time and more and more is coming up in
things like game programming. The idea is this: you have to allow for
the progress in technology as you work on a project that takes a
significant amount of time. For instance, if you work on an
accelerator that provides 2x performance improvement over current
hardware then for it to be useful you have to finish the project
before Moore's law for CPU performance overtakes the performance of
your project. Otherwise you could finish the project and find that
newer CPUs outperform your "accelerator".

This is why I chose a ridiculously large mantissa size for my project
:-). I realistically understand that I'm not going to complete this
project anytime soon. Plus with an FPGA design you're usually able to
make words as wide as you need for your application since everything
is ideally within the confines of a single chip and you don't need to
figure out how to get 1,024 bits out of the chip and into another chip
across a bus. Using a 1K bit mantissa gives me plenty of slack to
account for Moore's law progress in commercial CPUs.
--
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