Re: The reason of implementation of morphological operator in FPGA

In message <438C7490.2FD7@xxxxxxxxxxxxxxxx>, Peter T. Daniels <grammatim@xxxxxxxxxxxxxxxx> writes
Richard Herring wrote: 

In message <1133243655.314911.129840@xxxxxxxxxxxxxxxxxxxxxxxxxxxx>, TMU
<m.hajirahimi@xxxxxxxxx> writes
>hi
>I have studied some papers of implementation of morphological operator
>in FPGA and ASIC.
>I want to know the reason of  implementation of morphological operator
>in FPGA.
>Does FPGA implementation use only in test of our design?
>and what is the meaning of realtime processing? (the required speed of
>chip)
>can anyone help me?

You are in the wrong newsgroup. sci.lang is for discussion of (
(natural) languages and linguistics. You'd be better off finding a group
in the comp.* hierarchy - maybe comp.arch.fpga ?


That was the same poster who asked about "asic" yesterday. From the
header I thought it was asking about Basic English, but the message
contained the above sort of gobbledygook.

Application-Specific Integrated Circuits and Field-Programmable Gate Arrays.

--
Richard Herring
.

Relevant Pages