Re: Han's startling new set theory.

In article <1125496972.576822.44260@xxxxxxxxxxxxxxxxxxxxxxxxxxxx> "Randy Poe" <poespam-trap@xxxxxxxxx> writes:
....
> Your bit-by-bit analysis would imply that the time
> for a FLOP is proportional to the number of nonzero
> bits in the operands. I've worked with processors
> where multiplication time was variable, probably
> for that reason. But on the current generation that's
> not true.

It was even not true on some earler generation computers, say the
CDC Cyber 750 (dating from the 70s). An f-p add would take 3
cycles and an f-p multiply 4 cycles (48 bit mantissas). And of
these cycles, the first was used to issue and to split the
number in mantissa and exponent, and the last was used to
recombine the result and to store it in a register. And a cycle
was 20 nsec. Of course it requires quite a bit of hardware, the
previous model had a multiply of 57 cycles (while the add was
also 3 cycles).
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