Re: Leakage Current in Photodiode Circuit

In article <rbydnUNbIZFVk6PanZ2dnUVZ_u6rnZ2d@xxxxxxxxxxx>,
"Jarvis" <john.jarvis @ yahoo.co.uk> wrote:

Hi Folks -

I've got a question that is really more about electronics but probably only
a scientist skilled in electro-optics may appreciate. My question concerns
practical and realizable volume and surface resistivities seen in FR-4
printed circuit material.

Here is a description of the problem...

I'm building a ratiometric optical sensor. It has two channels of optical
signal that are divided with a beamsplitter, spectrally filtered, and
incident on two separate InGaAs photodiodes. The photodiode current then
goes to a charge integrating 20-bit A/D that has an input at "virtual
ground".

I'm finding that the ratio of the output of the two sensors is varying as a
function of overall light intensity. This is very bad as it indicates that
spectral ratio is changing when it isn't actually doing so.

For instance, when the overall light intensity drops by a factor of 2, the
ratio changes by 3%. When the light intensity drops by a factor of 13, the
ratio changes by 20%.

I'm presuming that the photodiodes are linear and the A/D is linear. At
least the spec sheets would suggest so.

I've pretty much determined that the problem is (mainly) due to leakage
current. I'm typically dealing with photodiode currents of about 2500 pA to
250 pA or lower. My leakage current would appear to be about 75pA.

I think that I've found a layout issue with the board that I would like to
blame but things still don't quite add up yet. This a four-layer board and
it has a power plane that runs under a 3 cm length of a 0.5 mm (20 mil)
sensor trace. The leakage current to the power plane suggests that the
leakage resistance is about 66 GOhm. By using the geometry and the
published minimum resistivity of FR-4 (8e7 MOhm*cm), I estimate the leakage
resistance should be 600 GOhm.

I would guess that at those current levels, you need to change the board
layout to provide guard conductors and layers just about everywhere.
Nodes at virtual ground can be guarded by grounded traces, while nodes
at other voltages need to be guarded by a trace driven by a voltage
follower at the voltage in question. The voltage follower input is
typically a RC filter so the guard voltage is ~DC.

With good guards, the surface and volume resistivity become of secondary
importance. The surface is easily contaminated, so it's best to
minimize the exposed area.

Phil Hobbes suggested cleaning with a domestic dishwasher, if the
components will allow it. I would go farther, by making the ability to
be run through a dishwasher a requirement during component selection.
If one uses a water-soluable flux for soldering, the dishwasher will
also remove all traces of the flux. Domestic dishwashers run at about
60 degrees C, which is comfortably within the temp range of industrial
components. The big issue is to ensure that all components are sealed
to prevent the entry of water. Switches, potentiometers, and connectors
are the usual issue. The data sheets will tell if the components are
washable.

Also, don't forget to design to withstand ESD (Electro Static
Discharge). The reason to bother in a one-off lab instrument is that
ESD can cause subtle damage, causing much bad data and wasted effort.
This is hard to add after the fact without compromising the low leakage,
and/or adding excess input capacitance. A typical approach is big zener
diodes from power rails to ground and/or each other, plus reverse-biased
high-grade signal diodes from non-power pins to the power rails and/or
ground. One can also put inverse parallel diode pairs from input to
guard, and reverse-biased diodes from guard to power rails.

Joe Gwinn
.

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