Re: Is time dilation real?

"Spaceman" <Realspace@xxxxxxxxxxx> wrote in message news:g7SdnW2W5fDDi0XeRVn-oA@xxxxxxxxxxxxxx
>
> "Greg Neill" <gneillREM@xxxxxxxxxxxxxxxxxx> wrote in message
> news:l8UBf.23315$ve.373015@xxxxxxxxxxxxxxxxxxxxxxxx
> | You don't seem to understand that the clock that
> | we see as running slow would be a perfectly good
> | clock to someone travelling along with it.
>
> No,
> I understand all that.
> It is you that does not seem to want to understand
> what clocks are supposed to do.
>
> If it changes rate of timing WTR another clock,
> one of them is wrong, simple as that
> Or even worse, both could be wrong.

Or they can both be right if the universe works
that way. And it does. This is the meaning of
the statement that time is relative.

>
> the change of rate is the problem
> timing in science should not be just accepting such
> a change and if it want to proceed it needs to fix
> such a timing problem and not just call it ok and work around it.

There is no fix. There is understanding how to make
measurements and apply the appropriate conversions
for frames of reference. That's the way the universe
seems to work. If relativity is correct, and according
to all tests performed so far it is, then there can be
no clock that will measure the same rate of time for all
observers. If you correct the clock for one observer,
it will still be wrong for others.

>
> If we just worked around clock malfunctions long ago,
> we would still have trains crashing into each other from
> clock malfunctions alone.

You are confusing accuracy with precision. Accurate
clocks on Earth are not affected by relativistic effects
to any degree that would impact mundane use.


.

Relevant Pages

  • Re: Spartan 3 clock to output tristate timing
    ... I'm a stickler for well defined I/O constraints so I see shoddy engineering on the part of the FPGA group, ... The Timing Analyzer within the Xilinx tool suite has a section at the end that summarizes data input setup and hold times as well as clock-to-out for all the various signals. ... I believe the clock and clock edge are included as well. ... As long as the design doesn't budge, ...
    (comp.arch.fpga)
  • Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic -
    ... "input setup/hold time" is the time required before a clock edge to ... Setup time is the time for the signal to be stable prior to ... live in isolation it is connected to outside devices that may have timing ... the calling module and in the signals used in the submodule. ...
    (comp.arch.fpga)
  • Re: Newbie frustration
    ... Many times this symptom is a result of a timing violation. ... I need to generate an internal clock:( ... SHIFTp = 13; ... I am using the async FIFO core from Xilinx's coregen. ...
    (comp.arch.fpga)
  • Re: clock recovery
    ... how can i implement clock recovery for fsk demodulator? ... then trust that the bit timing is sufficiently similar at the transmitter ... Then the receiver detects the beginning of a start bit, it counts off approximately half a bit time and checks again. ...
    (comp.dsp)
  • Re: In defence of Austin and Xilinx
    ... Maximum acceptable jitter is specified in the data sheet but must also be considered *internal* to the device since a poor set of switching I/Os and/or improperly bypassed and distributed rails can affect the amount of jitter seen by the time it gets to the global clock routing. ... A single via can induce 50ps or more of deterministic jitter on a highspeed line, and we won't even get into proper termination or the dozens of other gotchas in timing budget analysis. ...
    (comp.arch.fpga)